Hi,
for this week I like to propose the following schedule for lectures and practical work.
- 24.11.2021: 2nd UE (10:00 Uhr) Lecture Realtime-Systems in 01/322-1
- 25.11.2021: 1st UE (8:00 Uhr) Practical work Realtime-Systems and Systemprogramming for Group 1 in 01/k31
- 25.11.2021: 2nd UE (10:00 Uhr) Practical work Realtime-Systems and Systemprogramming for Group 2 in 01/k31
- 25.11.2021: 4th UE (14:30 Uhr) Introduction 2nd part of IDE for HW-/SW-/CoDesign for Group 1 in 01/221
- 25.11.2021: 5th UE (16:30 Uhr) Introduction 2nd part of IDE for HW-/SW-/CoDesign for Group 2 in 01/221
In addition, please find below the VHDL-Code of last practical work for HW-/SW-/CoDesign as a template for your work.
library ieee;
use ieee.std_logic_1164.all;
entity Test_XOR is
port (x, y : in std_logic;
z : out std_logic);
end entity;
architecture behave of Test_XOR is
begin
process (x,y)
begin
z <= x XOR y;
end process;
end behave;
Best regards
Ingo Chmielewski